Introduction to Secure Elements
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If you are into cryptography and cryptocurrencies, you have probably heard the saying that goes “not your keys, not your coins “. If an attacker gets hold of private keys just once, he basically has full control over your data, or in cryptocurrency context — your funds. Therefore, protecting keys is crucial.

As a rule of thumb, you should never keep your keys in the cloud, in a mail or your hard drive without encryption. This constraint already thins down the options for key storing to a few, including:

  • Memorizing the whole key. Although it sweeps away most of the attack vectors, this is a bad approach for obvious reasons.
  • Writing down the phrase on a piece of paper and storing it in a secure place. The written form of secret must preferably be in mnemonic encoded format that is less prone to mistakes and typos. This method is best when used as a back-up mechanism with other digital methods, and expanded with QR codes, crypto-steel or even embedding secrets inside a picture.
  • Storing the keys inside an external HDD or SSD. This method is safe as long as data on the drive, and the USB communication is encrypted and protected with passwords.
  • Storing the secret on mcu flash after encrypting the data. This approach comes with another liability which is the storage of the master key that encrypts the other sensible data. One can always memorize a relatively short password, run it through a Key Derivation or hashing function and use it as the master key. Since the same input is provided, both of these hardening functions will result in the same output.

Hardware security modules handle storing of sensitive data in an unorthodox way. Dedicated integrated circuits are designed for just one specific purpose - to enhance the overall security of the host system.
HSM consists of subsystems that are responsible for different operations, such as:


Having a true random generation function is crucial for key generation. With this function, the conditions to find the same number can’t be replayed. For example, if epoch time is used as a seed value for random generation, anybody could access the random value given the time of generation is known.
Secure elements come with uniform and independent random variable generator circuits embedded inside which can be used to create cryptographic keys of many kinds (ECC, RSA, Symmetric).


If the secret is created on the device, it is hidden inside the EEPROM memory of the secure chip which makes it impossible to back-up the secret. If the secret has to be persistent for a long amount of time it can be generated and written on a paper wallet as described above, then it can be injected into the device. This approach is robust, as well as safe. Same EEPROM memory can also be used for general storage purposes.


Ownership of a private key can be forged inside specialized hardware through digital signatures. This is extremely useful in situations such as the creation of blockchain transactions or TLS certificates. The private key never leaves the silicon during operations that require the usage of private keys.


Just like digital signature generation, key derivation from a single seed (HKDF) or encryption can be done on chip. Once the symmetric key has been provisioned into the device, the rest of the cryptographic operations are done on chip.
After the provisioning phase, secrets never leave the device. Operations such as signing, verifying, encrypting, key derivation, certificate generation are done on chip. The output of these operations are fed back to the host mcu through the supported physical layer without exposing the secret key behind. Combining this with an encrypted physical layer creates a bulletproof solution.


The need for hardware level security is a rising trend since IoT has become a part of our lives. Specialized hardware and software enclaves carry the trust layer from user space to kernel level, creating an isolated and hard to tamper with environments for sensitive data operations. Since crypto-accelerator chips are specifically built for this type of operations, they are faster, more powerful and efficient than their software implementations. This fits perfectly into the IoT concept where devices are generally battery powered and not as performant as an x86 machine. Let’s explore the merits and risks of introducing a secure element to your system.

Secure elements are being used in various environments, such as:

  • Hardware cryptocurrency wallets in generating and storing key pairs.
  • Payment systems like Chip and PIN cards for storage of secrets and on-chip cryptographic operations.
  • Integrity checks during boot loading to check if the software being loaded is the intended one through hashing functions and ECDSA (Secure Boot).
  • Authenticity checks with TLS handshake to only communicate with the intended host.

Secure devices come with a general purpose microcontroller and a companion secure element chip equipped with a crypto-accelerator. These two are connected to each other mostly through i2c, SMBUS on the physical layer. T=1 or Smart card application protocol data unit (APDU) on the second layer.

In essence, a secure element is a black-box with a closed sourced software to protect the vendor IP and provide security through obscurity. It comes equipped with a crypto logic and sort of operating systems of their own, the middleware code which runs above the vendor specific operating system primitives and acts as an interface between the physical world and the secure element.

The system is as secure as its weakest link. If the channel between SE and the host mcu is not encrypted, this poses a huge security threat. This weakness can be leveraged against even with cheap hardware and unsophisticated methods, unlike side channel attacks.


Although secure elements may seem superior on many levels to the other methods, its superiority in functionality and extra security doesn’t come cheap. It exposes the system to a new spectrum of attack vectors such as side channel attacks which use the electromagnetic noises emitted by the device of extract sensitive data, physical attacks unless the chip is tamper proof, need for channel encryption that encrypts the communication layer between the secure element and the host-PC.

Some of these possible weaknesses can be overcome by efficiently using the provided vendor middleware while the rest has to be implemented as a feature by the vendor. Main HSM developers to choose from are NXP, (A71CH, se050), Microchip (atecc608a, atecc508), Optiga (Trust-X), Atmel. All exist with different features and varying software complexities.

Finally, here is a few caveats for users considering to deploy a hardware security module into their system:

  • Closed source nature of secure elements is definitely a downside in today’s world of software where transparency and auditability are everything. This may raise concerns for possible intentional back doors or badly implemented software. This is why some wallets like Trezor use the encrypted storage of their mcu EEPROM rather than a dedicated hardware.
  • Secure element integration increases both hardware and software complexity leading to a less agile system.
  • Other shortcomings of the secure element that have been mentioned above can be only fixed on the vendor implementation side. This thins down the options for the developer.
  • Porting the secure element to a different architecture can be challenging especially in bare-metal environments.

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